1. Field of the Invention
The present invention generally relates to an image forming apparatus, an electric apparatus, and a recording control method.
2. Description of the Related Art
One type of a Spread Spectrum Clock Generator (SSCG) is used for preventing Electro-Magnetic Interference (EMI) for avoiding electro-magnetic noise emitted from an electric apparatus and an image forming apparatus. By modulating the frequencies of clock signals with the one type of SSCG, it is possible to decrease a peak value of a frequency spectrum of the clock signal. With this, it is possible to reduce the emitted electromagnetic noise.
In avoiding electro-magnetic noise, EMI prevention using the one type of SSCG can substantially reduce manufacturing costs of electric apparatuses and image forming apparatuses while maintaining an EMI reducing effect very well. On the other hand, there is a system which cannot allow frequency modulation using an SSCG. An example technique using EMI prevention with the SSCG is provided to reduce a diffuse width with the SSCG down to a tolerance level or separate a system causing operating trouble to thereby apply the EMI prevention with the SSCG only to a system causing no operating trouble.
The technique of Patent Document 1 is provided to reduce a cost for the EMI prevention by enabling a use of the SSCG for the EMI prevention in an image reading apparatus. In this, a timing circuit of the image reading apparatus is divided into an analog clock generating circuit and a digital clock generating circuit. A reference clock signal from a reference clock oscillator is used in the analog clock generating circuit, and a spread spectrum clock from a SSCG is used in the digital clock generating circuit.
According to the technique of EMI prevention using the one type of SSCG, the diffusion width with the SSCG is limited by a jitter standard value of a Phase Locked Loop (PLL) circuit when the PLL circuit is mounted in an application specific integrated circuit (ASIC) or a Field Programmable Gate Array (FPGA) in an image forming apparatus including a control board in which the ASIC or the FPGA is mounted. Therefore, in the example technique, the diffusion width with the SSCG may be lowered to the tolerance level based on the jitter standard value of the PLL circuit. As a result, there may be a problem in obtaining a sufficient EMI reducing effect.
In the technique described in Patent Document 1, there are similar problems in which the diffusion width with the SSCG may be limited by the jitter standard value of the PLL circuit and a sufficient EMI reducing effect is not obtainable.
Patent Document 1: Japanese Laid-Open Patent Application No. 2001-094734.